This document relates to transferring and storing data in multicore and multiprocessor computers.
A multiple processor system can include multiple processor cores on a chip interconnected by an on-chip communication bus, or multiple discrete processor cores within a device interconnected by a communication bus, for example. Data can be transferred among the processor cores by sending data over the bus directly from a sender to a receiver, or by storing the data in a memory accessible to both the sender and receiver, for example.
Cache coherence is a useful mechanism in multiple processor systems to provide a shared memory abstraction to the programmer. When multiple processor cores cache a given shared memory location, a cache coherence problem arises because a copy of the same memory location exists in multiple caches. A cache coherence protocol guarantees that that memory location has a consistent view across all processor cores. There are many models of what a consistent view is, and one example is sequential consistency. Another is weak ordering. In each of these models, the coherence protocol prescribes a legal order in which memory locations can be acquired by and updated by various processors.